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W971GG6JB
8.2.2.3
Extend Mode Register Set Command (2), EMR (2)
( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "H", BA2 = "L" A0 to A12 =
Register data)
The extended mode register (2) controls refresh related features. The default value of the extended
mode register (2) is not defined, therefore the extended mode register (2) must be programmed during
initialization for proper operation.
The DDR2 SDRAM should be in all bank precharge state with CKE already high prior to writing into
the extended mode register (2). The mode register set command cycle time (t MRD ) must be satisfied to
complete the write operation to the extended mode register (2). Mode register contents can be
changed using the same command and clock cycle requirements during normal operation as long as
all banks are in the precharge state.
BA2 BA1 BA0 A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0* 1
1
0
0* 1
SELF
0* 1
Extended Mode Register (2)
BA1 BA0
MRS mode
A7
High Temperature Self Refresh Rate Enable
0
0
1
1
0
1
0
1
MRS
EMR (1)
EMR (2)
EMR (3)
0
1
Disable
Enable* 2
Notes:
1. The rest bits in EMR (2) is reserved for future use and all bits in EMR (2) except A7, BA0, BA1 and BA2 must be programmed
to “ 0 ” when setting the extended mode register (2) during initialization.
2. When DRAM is operated at 85°C < T CASE ≤ 95 °C or 105°C the extended Self Refresh rate must be enabled by setting bit
A7 to “ 1 ” before the Self Refresh mode can be entered.
Figure 4 – EMR (2)
Publication Release Date: Sep. 24, 2013
- 13 -
Revision A09
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